USB2.x DEVICE IIP

Universal Serial Bus 2.x Device IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech USB2.x DEVICE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Perfect for consumer electronics, peripherals, and embedded IoT devices. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Certified Interoperability: Extensive testing against standard USB hosts and devices to guarantee plug-and-play compatibility.

Highly Configurable: Flexible endpoint configuration and FIFO sizing to optimize area vs. performance trade-offs.

Low Power Modes: Aggressive power management supporting Suspend/Resume and remote wakeup capabilities.

Legacy Support: Backward compatibility ensuring seamless operation with older USB revisions.

FEATURES

Compliant with USB 2.0 specification.
Three caching models: no caching, micro-frame caching and frame caching
NAK counter to limit unnecessary memory accesses
Descriptor and data pre-fetch, pre-compute and cache
Attach, reset signaling and suspend/resume.
Supports UTMI and ULPI transceivers.Operates at High-speed (480 Mbps), Full-speed
(12Mbps) and Low-speed (1.5 Mbps).
Enumeration of low-speed, full-speed, and high-speed devices.
All USB 1.1 transfer types are supported.
Supports Interrupt/Bulk/Isochronous/Control Transfers.
Supports High Bandwidth Interrupt and Isochronous endpoints.
(Cyclic Redundancy Check)CRC16 checking and generation for HS/FS/LS data packets.
(Cyclic Redundancy Check)CRC5 generation and checking for Tokens.
Supports Protocol Layer Error Handling.
Supports USB Suspend state and supports remote wakeup devices.
Supports the clock gating and multi-power-well support.
Supports UTMI 8 bit mode interface.
Supports Low Power Management and fsls serial mode.
Supports 16 bidirectional endpoints.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple interface allows easy connection to microprocessor/microcontroller
devices.
Slave mode operation is used to trigger responses to USB 2.0 transactions. Available as additional Feature at extra cost

ISO26262 Automotive safety(ASIL B/D)
XML Support

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the USB2.x DEVICE IP. Ports of core module are the top level ports for the USB2.x DEVICE IP.

PROTOCOL LAYER: protocol layer module takes care of packet disassembler and packet assembler and data processing in protocol engine.

CTRL: Ctrl module will take care of all standard device requests with respect to endpoint zero.

ROM1: Rom will store the descriptor details of endpoint zero from which the data can be retrieved.

ENDPOINT PROCESSOR: Endpoint processor will organize the endpoint config details with respect to transfer type, config type, and config size. It then mediates the data read and write and other signals from fifo.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency
TSMC 28nm	8.10K	60MHz

FPGA Device and Family	Logic Resources	System Clock Frequency
AMD Virtex-7 FPGA(xc7vx485tffg1761-2)	1307 LUT's	60MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.