CORE: Core module interconnects all the sub-modules in the Ethernet 2.5G/5G/10G BaseT1 PCS IP. Ports of core module are the top level ports for the Ethernet TSN 2.5G/5G/10G BaseT1 IP.
64/65B ENCODER: Two 32 bit XGMII input transfers to 64/65B Encoder. It will encoded as one 65 bit transmission block that contains Control characters and block type field.
OAM TX: Encoded 65-bit blocks are aligned into groups of 50 blocks. The contents of each group are contained in a vector tx_group50x65B. 10-bit OAM field is appended to form a 3260-bit block. This OAM field is used to monitoring the link operation.
RS FEC ENCODER: The encoder processes 326 ten-bit RS-FEC message symbols to generate 34 ten-bit RS-FEC parity symbols, which are then appended to the message to produce a codeword of 360 ten-bit RS-FEC symbols.
SCRAMBLER: Output of the RS FEC encoder data will be grouped and scrambled using addictive scrambler logic.
GRAY MAPPER: The scrambled data will be gray coded and given as PAM4 symbol output.
SELECTABLE PRECODER: It will precode the gray coded symbols based on precode selection received from the link partner.
PAM4 ENCODING: It will encode each precoder output symbol to one of four PAM4 levels as -1, +1, -1/3, +1/3.
FRAME SYNC: It obtains block lock to the PHY frames (PAM4 Stream) during PAM2 training using synchronization bits provided in the training frames.
DEMAPPER: It demap the PAM4 symbols into scrambler output data.
DESCRAMBLER: Descramble the data using addictive scrambler logic.
RS FEC DECODER: Received Frames are decoded with Reed-Solomon error correction. Frames that cannot be corrected are marked with error symbols by the decoder. The RS-FEC decoded frame is then separated into a 10-bit OAM field and 50 64B/65B blocks.
64/65B DECODER: It will decode the 65 bit block into two 32 bit XGMII data(2.5G/5G/10G data rate)
AN FSM: AN FSM module is used to implement for exchanging ability between local device and link partner.
CSR: CSR module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
