CORE: Core module interconnects all the sub-modules in the ROE IP. Ports of core module are the top level ports for the ROE IP.
TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.
TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.
GMII/MII TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.
FLOW CTRL: Initiating the Transmission of pause frame based on the Receive FIFO's threshold or External requests.
PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.
GMII/MII RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.
RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.
RX CTRL: Receive Control block processes the data from MAC 1G interface and push the data into RX ASYNC FIFO
MAPPER: It takes the RAW synchronous data from the radio equipment and packages it for asynchrounous Ethernet transmission. It wraps the time-domain samples or control datainto RoE packet. It provides the structure-Agnostic or Structure-Aware
DEMAPPER: It exacting the radio data from the Ethernet stream to reconstruct the original synchronous interface. It uses a buffer to smooth out arrival times before passing data to the radio interface.
MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.
CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
