CORE: The top-level integration layer that interconnects all sub-modules and exports the primary IP interfaces to the system SoC.
CSR: CSR contains all Control and Status Registers(CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.
HPD PROCESS: This Module monitors Hot Plug Detect(HPD) signal and identifies IRQ and unplug events, and coordinates the required control actions through the AUX interface.
AUX FSM: It Manages the auxiliary channel protocol by initiating AUX read/write transactions and validates responses for Link Training.
LINK TRAINING: Link training module negotiates and maintains the physical link with the receiver through automated clock recovery and channel equalization procedures.
LINK LAYER: The link layer includes the link FSM, Video packer, and SDP/Audio packer.
LINK FSM: Link FSM is responsible for formatting the outgoing audio/video stream by inserting required fill symbols to maintain stream synchronization.
VIDEO PACKER: Video packer formats incoming pixel data based on configured colorimetry and bit-depth(BPC), ensuring precise alignment within the DisplayPort stream.
SDP/AUDIO PACKER: It constructs Secondary Data Packet(SDP) headers and packs audio samples with the required metadata, forming an SDP packetized audio stream based on the configured sample rate and channel configuration.
DSC: It is an optional module which implements VESA Display Stream Compression to reduce pixel bandwidth requirements enabling efficient transmission of high-resolution video over the DisplayPort link.
HDCP: It is an optional module which provides end-to-end content protection via secure authentication, key exchange, and high-speed data encryption.
LOGICAL PHY: The physical coding sublayer(PCS) comprising the Scrambler, 8b10b or 128b132b encoders, RS-FEC, and Gearbox logic.
SCRAMBLER: The scrambler employs a polynomial seed to scramble Main-Link data, significantly reducing Electro-Magnetic Interference(EMI) prior to line encoding.
8B10B ENCODER: It Converts 8-bit data into 10-bit symbols to ensure DC balance and adequate transition density through running disparity control.
128B132B ENCODER: It Provides high-efficiency line encoding for UHBR rates, mapping 128-bit data blocks into 132-bit transmission blocks for maximum throughput.
RS-FEC(254,250): It is an optional module that performs Reed-Solomon(254,250) encoding to detect and correct transmission errors.
GEARBOX: This Module converts internal link layer data width to PHY interface widths of 10-bit,20-bit,40-bit and 80-bit depending on the PHY configuration.
