Automotive-Grade CAN & CAN FD Controller IIP

High-Reliability Automotive Connectivity

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Automotive-Grade CAN & CAN FD Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES

Full compliance with CAN 2.0 A/B (ISO 11898) and CAN FD 1.1 specifications.
Optimized support for SAE J1939 and AutoSAR software architectures.
High-speed data rates: Up to 1 Mbps for Classic CAN and 5 Mbps for CAN FD.
Comprehensive frame support: Data, Remote, Error, and Overload frames.
Flexible addressing: Supports both 11-bit (Standard) and 29-bit (Extended) identifiers.
Advanced error management: Integrated hardware detection for bit, stuff, CRC, form, and acknowledgment errors.
Deterministic performance: Supports Time-Triggered CAN (TTCAN) operation (ISO 11898-4).
Functional Safety ready: Designed to meet ASIL B and scalable to ASIL D requirements (ISO 26262).
Low-latency architecture with configurable FIFO buffering and acceptance filtering.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the CAN Controller IP. Ports of core module are the top level ports for the CAN Controller IP.

TFSM: TFSM Module is responsible for driving CAN frames through Bus. Standard and Extended Message formats transactions for both CAN / CAN FD frames. Response frame transactions, If remote frame was received.

RFSM: RFSM Module is responsible for sampling CAN frames through Bus and also for Error detection.

TIMING: TIMING Module is responsible for Bit timing characteristics of CAN protocol.and also for BRS(Bit rate switching) in CAN FD Scenarios.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	14.21K	100MHz
TSMC 12nm	20.80K	100MHz
TSMC 90nm	20.79k	100MHz
TSMC 130nm	20.79K	100MHz
TSMC 180nm	21.84K	100MHz
GF 180nm	15.17K	100MHz
SMIC 40nm	15.23K	100MHz
UMC 55nm	24.58K	100MHZ

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	2202 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.