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SLVS-EC Transmitter IIP

Scalable Low Voltage Signaling - Embedded Clock Transmitter IIP

SLVS-EC Transmitter IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SLVS-EC Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • SLVS-EC Transmitter v3.0
  • Fully compliant with the SLVS-EC v3.1 specification and ensures standard-adherent operation across all supported configurations.
  • Backward compatible with v3.0/v2.0/v1.0.
  • Dynamically supports lane configurations of 1, 2, 4, 6, 8.
  • Supports baud grades up 1152 Mbps to 12500 Mbps.
  • Supports configurable input pixel processing of 1, 2, 4, 8, 16 and 32 pixels per clock.
  • Supports multiple system topologies between CIS and DSP:
    • Basic Topology
    • Multiple I/F Topology
    • Multiple CIS Topology
  • Supports with the RAW pixel data formats of 8, 10, 12, 14 and 16.
  • Dynamically supports Lane skew.
  • Supports Embedded data transfer.
  • Compatible with Multiple stream transfer.
  • Performs 8b/10b Encoding and is compatible with GCC Symbol Encoding.
  • Supports Error Correction Codes(ECC) and Cyclic redundancy checks(CRC).
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

PIXEL TO BYTE CONVERTOR: Converts the incoming pixel data into a standard byte stream based on the configured bits-per-pixel.

LINK FSM: Cycles through a series of states to manage the incoming data from the sensor.

LANE DISTRIBUTOR: Distributes the formatted data from the Link FSM across the configurable lanes as 1,2,4,6 and 8.

LOGICAL PHY: Transmits the required Phy control codes in synchronization with the packet data and performs 8b10b encoding.

ENCODER: Converts the incoming 8bit data into 10bit encoded symbols and maintain DC Balance to across the link.

GCC: Implements specialized Channel encoding by converting standard data symbols into GCC link and PHY control symbols.

LANE SKEW: Inserts skew between the parallel data lanes to meet interface timing requirements.

GEARBOX: Converts the constant 10bit input into variable 20bit, 40bit or 80bit parallel output for the physical transmission lanes.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyByte Clock FrequencySerdes Clock Frequency
TSMC 28nm142.98K100MHz148.5MHz62.5MHz62.5MHz
SMIC 40nm149.77K100MHz148.5MHz62.5MHz62.5MHz
UMC 55nm279.92K100MHz148.5MHz62.5MHz62.5MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyByte Clock FrequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e24961 LUT's100MHz148.5MHz62.5MHz62.5MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.