ETHERNET SGMII PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET SGMII PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Implements PCS functions of the Cisco SGMII Specification, Revision 1.9
Supports (G)MII data rates of 1Gbps, 100Mbps, 10Mbps
Supports Management Interface Port for control and maintenance
Management registers accessible through MDIO
Supports data rate adaptation for 10M/100M speed
Supports TBI Interface
Supports Frame encapsulation at Transmit PCS and de capsulation at Receive PCS
Supports synchronization on Receive PCS
Supports generation of carrier sense and collision detection to GMII Interface
Supports IEEE Standard 802.3.2022 - Clause 37 Auto negotiation
Supports IEEE Standard 802.3.az Energy Efficient Ethernet(EEE)
Supports Loopback functionality
Optional support for Auto negotiation with Next page
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET SGMII PCS IP. Ports of core module are the top level ports for the ETHERNET SGMII PCS IP.

TX FSM: TX FSM module is used to implement both encapsulation and 8B/10B encoding of the data.

TX RATE ADAPTATION: TX Rate Adaptation module receives data from MAC via MII/GMII Interface. It will convert the data from 2.5MHz/25MHz frequency to 125MHz frequency as per the configuration.

ENC8_8B_10B: To attain DC balance and for clock recovery,ENC8_8B_10B module is used for encoding the eight bit data into more transition ten bit code groups.

TX LPI TIMER: TX LPI Timer module implements the LPI sleep, quiet and refresh timers when LPI is asserted.

RX FSM: RX FSM module is used to maps the 8bit data with the GMII signals.

RX RATE ADAPTATION: RX Rate Adaptation module adapts the data rates for received data.It will convert the data from 125MHz frequency to 2.5MHz/25MHz frequency as per the configuration.

RX LPI TIMER: RX LPI Timer module implements the LPI quiet, wake and wake fault timers with the LPI reception.

CARRIER SENSE: The carrier sense signal is asserted when if any one of the transmitter starts transmitting frame or receiver starts receiving frame.

SYNC FSM: SYNC FSM module is used to synchronize the 10bit block from the incoming code group based on the Comma Detect.

COMMA DETECT: COMMA DETECT module is used to detect the valid code group on the receive PCS for acquiring alignment with the byte boundary.

DEC8_8B_10B: DEC 8B/10B module is used for decoding the ten bit code groups into eight bit data once synchronization lock is attained.

AN FSM: AN FSM module is used to implement for exchanging ability between local device and link partner.

CSR: CSR module has Control Status registers that controls the IP. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency
TSMC 28nm	65.86K	167MHz	125MHz	125MHz
UMSC 55nm	92.86K	167MHz	125MHz	125MHz
SMIC 40nm	77.86K	167MHz	125MHz	125MHz

FPGA Device and Family	Logic Resources	Clock Frequency	MAC Clock Frequency	Serdes Clock Frequency
Kintex 7,1495 LUT's	167MHz	125MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.