CORE: Core module interconnects all the sub-modules in the eCPRI IP. Ports of core module are the top level ports for the eCPRI IP.
TIMESTAMP UNIT: This module captures the time from the counters when any of the PTP event or general messages transmit from MAC TX.
PACKET CLASSIFIER:
The packet classifier parses the incoming Ethernet frame to identify the types of incoming packets. Packet classifier redirects eCPRI packets to next component for further processing. ETHERNET HEADER INSERTION AND REMOVAL: The Ethernet header insertion block inserts Ethernet header to incoming eCPRI packet on TX path. Optionally it can insert IPv4/UDP headers to the packet based on the configuration. Ethernet header removal block removes Ethernet header to incoming eCPRI packet on RX path. Optionally it can remove IPv4/UDP headers to the packet based on the configuration selected.
CONCATENATION/DE-CONCATENATION:
The Concatenation/De-concatenation blocks of the eCPRI IP implements concatenation logic of the eCPRI messages into single Ethernet frame or single IP/UDP packet. The sink concatenation sideband signal identifies packets that required concatenation. HEADER MAPPER/DE-MAPPER: The Header mapper/De-mapper block append or remove the eCPRI common header from the eCPRI message.
eCPRI IWF TYPE 0: The eCPRI IWF type 0 converts eCPRI message type to CPRI protocol. This block allows the interface between eCPRI transport network with CPRI node(s).
eCPRI MESSAGE 5 PACKET PARSER: This block is responsible to initiate and calculate the eCPRI one-way delay measurement on the transport link. The eCPRI one-way delay measurement can be performed without (one-step) or with a follow-up message (two-step).
PACKET QUEUE: This block is responsible to stage user incoming Ethernet frames (e.g., Control and Management packets, synchronization packets & etc) and arbitrate with eCPRI packets. These user Ethernet frames share the same Ethernet link with eCPRI packets. eCPRI IP does not encapsulate Ethernet header to these frames.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
