The SivaKali Tech I2C Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Compliant with I2C version 7.0 specification
Supports HCI and Non HCI Interface
Full I2C Master Functionality
Supports Start, Repeated start and Stop for all possible transfers Supports 7bit/10bit Addressing
Supports following speed modes
Standard mode - 100Kbits/s
Fast mode - 400Kbits/s
Fast plus mode - 1 Mbits/s
high-speed mode - 3.4 Mbits/s
Ultra Fast mode - 5 Mbits/s (Unidirectional data transfer)
Supports General call address handling Supports START byte generation and handling
Supports Bus clear feature
Supports Device ID feature
Supports CBUS, SMBUS, PMBUS Compactability
Supports Master arbitration and clock stretching
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the I2C Master IP. Ports of core module are the top level ports for the I2C Master IP.
PRESCALAR: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I2C.
FSM: FSM module process the commands once pending request from CSR and the bus is enabled. For Example: I2C write, Master FSM will send Slave address, R/W bit, Write data and waits for ACK/NACK from Slave.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 12nm
26.61K
50MHz
TSMC 28nm
16.52K
50MHz
TSMC 90nm
23.72K
50MHz
TSMC 130nm
23.72K
50MHz
TSMC 180nm
24.95K
50MHz
GF 180nm
19.28K
50MHz
UMSC 55nm
29.14K
50MHz
SMIC 40nm
17.40K
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD Xilinx Genesys2
51685 LUT's
50MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
