The SivaKali Tech SMBUS Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with SMBus version 3.3.1 specification
Supports HCI and Non HCI Interface Full SMBus Master Functionality
Supports command code Protocols
Write Byte/Word
Read Byte/Word
Process Call
Block Write/Read
Block Write-Block Read Process Call
Write 32 Protocol
Read 32 Protocol
Write 64 Protocol
Read 64 Protocol
Supports Non command code Protocols
Quick Command Protocol
Send Byte Protocol
Receive Byte Protocol
Supports Address Resolution Protocol
Supports SMBAlert signal and SMBsus signal
Supports Packet Error Checking
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the Master IP. Ports of core module are the top level ports for the Master IP.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for SMBUS.
FSM: FSM module process the commands once the pending request from CSR and the bus is enabled. For write, Master FSM will send Slave address, R/W bit, Write data and waits for ACK/NACK from Slave.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 12nm
57.16K
50MHz
TSMC 28nm
38.66K
50MHz
TSMC 90nm
54.58K
50MHz
TSMC 130nm
54.58K
50MHz
TSMC 180nm
56.23K
50MHz
GF 180nm
40.28K
50MHz
UMSC 55nm
741.23K
50MHz
SMIC 40nm
64.80K
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD Xilinx Genesys2
51685 LUT's
50MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
