The SivaKali Tech ONE WIRE Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Supports One Wire implementation of Dallas/Maxim Semiconductor
Supports following commands of One wire Interface of Dallas/Maxim
->Read ROM
->Skip ROM
->Match ROM
->Search ROM
->Read Memory
->Extended Read Memory
->Write Memory
->Extended Write Memory
->Write Status
->Read Status
Glitch suppression (optional).
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
Implemented in Unencrypted Verilog, VHDL and SystemC.
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the ONE WIRE Master IP. Ports of core module are the top level ports for the ONE WIRE Master Controller IP.
FSM: FSM module decodes the ONE Wire protocol commands and process the commands. This blocks implements all the features of ONE WIRE specs
PULSE: Pulse module is used to detect the reset and process it. And, This module detects logic 0 and logic 1.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 28nm
9.55K
40Mhz
UMSC 55nm
10.09K
40Mhz
SMIC 40nm
280K
40Mhz
FPGA Device and Family
Logic Resources
Clock Frequency
Virtex Ultrascale +
1487 LUT's
40 MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
