AHB DECODER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech AHB DECODER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.

Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.

High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.

Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.

FEATURES

Compliant with AMBA AHB specification
Supports configurable number of AHB Master
Supports configurable number of AHB Slave types, burst transfers and response types
Support for all the transfer sizes
Supports configurable Endianness of the Data bus
Supports feature of decoder to decode address from master and to map to the respective slave on the AHB Channel
Supports multiplexor to select the read data slaves and to route to respective AHB Master on the bus
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

FUNCTIONAL DESCRIPTION

CORE: Core module performs all the below functionalities in the AHB DECODER IIP. Ports of core module are the top level ports for the AHB DECODER IIP.

AHB SLAVE: AHB Slave is used to respond to a read or write operation within a given address-space range. It accepts address and control from the master and returns data/response.

AHB MASTER: AHB Master is use to initiate read and write operations by providing an address and control information.

AHB DECODER: The AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	3.75K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	12500 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.