NAND FLASH IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech NAND FLASH IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.

Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.

Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.

PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.

FEATURES

Implemented in Unencrypted Verilog, VHDL and SystemC
Supports NAND Flash memory devices from all leading vendors.
Supports 100% of NAND FLASH protocol standard of HY27UH08AG(5/D)M.
Supports all the NAND FLASH commands as per the specs.
Provides cost effective solutions for mass storage applications.
Supports NAND interface of x8 width.
Supports multiplexed Address/Data.
Supports memory cell array of (2K+64) Bytes *64 Pages*16,384 Blocks.
Supports page size of (2K + 64 spare) Bytes for x8 device.
Supports Block size of (128K + 4K spare) Bytes for x8 device.
Supports page read/program.
Supports Copy back program mode for fast page copy without external buffering.
Supports cache program mode to improve the program throughput.
Supports Fast block erase time of 2ms.
Supports status register.
Supports Electronic signature.
Supports Chip enable don’t care.
Supports Hardware data protection.
Supports Data integrity of 100,000program/erase cycles.
Implemented in Unencrypted OpenVera, Verilog, SystemC and SystemVerilog.
Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
Fully synthesizable
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

ASIC AND FPGA IMPLEMENTATION

Target Node	Max Frequency	Area/Resources
7nm FinFET	> 1.2 GHz	< 0.1 mm2
28nm HPC+	> 800 MHz	< 0.25 mm2
FPGA (UltraScale+)	> 400 MHz	~5,000 LUTs

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.