The SivaKali Tech Micro Second Channel Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Implemented in Unencrypted Verilog, VHDL and SystemC
Supports multiple external power device connection
Supports the following data channels
Upstream Channel
Downstream Channel
Supports two types of downstream frame
Command frames
data frames
Supports two modes of transmission
Triggered mode
Data repetition mode
Supports the following registers
Command register
Diagnosis register
Status register
Configuration register
Control register
Standard asynchronous serial frames
Programmable upstream data frame length (16 or 12 bits)
Parity error checker
8-to-1 input multiplexer for SDI lines
Built-in spike filter on SDI lines
Programmable delay of the receive interrupt after the last stop bit (0 or 1 bit
time)
Supports the lock / unlock of configuration register.
Asynchronous Baud Rate Adjustment Block
64-bit data frames extension
Fully compatible with the 32-bit data frames
Supports MSC Plus specifications
Supports Manchester encoding in both transmit and receive paths
Supports two layers concept in MSC Plus mode. Instead of alternating like standard MSC, the commands frames are sent as part of the data frame. This indicates that the commands are one layer above the data being transmitted.
Supports the transmission of UART bits at the start of the frame in MSC Plus mode
Supports bit rate up to 100Mbit/s in MSC Plus mode
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the MSC Master. Ports of core module are the top level ports for the MSC Master IP.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ABRA: This module implements Asynchronous Baud Rate Adjustment Block. Basically ABRA mode has dedicated prescaler and mode control to select ABRA operation.
DOWNSTREAM: This module implements downstream statemachine. This module is used to transfer Downstream command and data frames.
UPSTREAM: This module implements downstream statemachine. This module is used to transfer Upstream 12bit and 16bit data frames.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for transmission and reception of MSC Master.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
Protocol Clock Frequency
TSMC 28nm
8.09K
200MHz
400MHz
UMSC 55nm
7.44K
200MHz
400MHz
SMIC 40nm
13.45K
200MHz
400MHz
FPGA Device and Family
Logic Resources
System Clock Frequency
Protocol Clock Frequency
AMD-xcvu9p-flga2104-2L-e
12525 LUT's
200MHz
400MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
