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ETHERNET 1000BASET PCS IIP

ETHERNET 1000BASET PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 1000BASET PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Supports IEEE 802.3.2022 standard specifications Clause 40
  • Supports GMII interface with 1000Mbps speed
  • Supports Full duplex operation
  • Supports 33 bits side-stream scrambler and descrambler
  • Supports 4D-PAM5 encoding scheme
  • Supports IEEE Standard 802.3.2022 Clause 28 Auto negotiation
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet 1000BASET PCS IIP. Ports of core module are the top level ports for the Ethernet 1000BASET PCS IIP.

PCS TX FSM: The PCS Transmit FSM module does the Frame encapsulation and align the MAC data with the control indication.

PCS SCRAMBLER: The PCS Scrambler module uses the 33-bit side stream scrambler which randomizes the transmit bit stream so that it ensures DC balance.

TX ENCODER: GMII data is encoded using an 4D- PAM5 technique into a vector of four quinary symbols until tx_enable is de-asserted. It will encode the SSD and ESD symbols based on the TX_EN assertion and deassertion.

PAM5 MAPPER: The PAM5_MAPPER module converts coded digital symbols into PAM5 levels (such as -2,-1,0,+1,+2) before PMA signal processing and transmission.

PAM5 DEMAPPER: The PAM5 DEMAPPER module converts the received PAM5 symbols (from the PMA RX) into digital symbols that can be processed by the trellis decoder.

RX DECODER: The RX Decoder module recovers the original scrambled bit stream from received data using PAM5-4D decoding.

PCS DECRAMBLER: It descrambles the data using 33 bit side stream descrambler logic to provide the PCS data and control bit stream.

PCS RX FSM: The PCS Receive FSM module interprets the descrambled PCS bit stream, detects the Ethernet frame boundaries, align bytes, and delivers valid receive data and control signals to the MAC

AN FSM: AN FSM module is used to implement for exchanging ability between local device and link partner.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencyMAC Clock FrequencySerdes Clock Frequency
TSMC 28nm73.48K167MHz125MHz125MHz
UMSC 55nm97.24K167MHz125MHz125MHz
SMIC 40nm85.79K167MHz125MHz125MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e12246 LUT's167.625MHz125MHz125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.