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HDCP 2.x Receiver IIP

High Bandwidth Digital Content Protection 2.x Receiver IIP

HDCP 2.x Receiver IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HDCP 2.x Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Essential for safeguarding sensitive data in government, financial, and IoT applications. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Side-Channel Resistance: Design hardened against DPA (Differential Power Analysis) and other side-channel attacks.

High Performance: High-throughput encryption/decryption engines to match line-rate speeds of modern interfaces.

Standard Compliance: Fully compliant with NIST and ISO security standards.

Easy Integration: Standard system bus interfaces for straightforward integration into secure enclaves.

FEATURES
  • HDCP 2.x receiver IIP
  • Fully compliant with the HDCP version 2.3 specification and ensures standard-adherent operation across all supported configurations
  • Supports HDCP Receiver functionality for Display Port, HDMI and MHL content interfaces.
  • Supports configurable output cipher symbols per clock of 1, 2, 4, 8 or 16
  • Supports AES with a 128-bit key length(AES-128).
  • Supports RSA decryption for secure authentication.
  • Supports User loadable keys for the authentication process.
  • Allows cipher text generation via dedicated hardware or API during the authentication process.
  • Cipher text can be generated using Hardware/API during Authentication Protocol.
  • Fully Supports all HDCP Authentication Protocols and key exchange mechanisms including:
    • Authentication and Key Exchange
    • Locality Check
    • Session Key Exchange
    • Link Integrity Check
    • Key Derivation
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

HMAC SHA256: Implements HMAC-SHA256 algorithm to generate and verify message authentication codes during Authentication and Key exchange(AKE), Locality check and session key derivation.

SHA256: Computes SHA-256 hash values required during HDCP authentication and key derivation process.

RSA: Implements RSAES_OAEP decryption to process secure key exchange parameters recieved from the transmitter during AKE.

RNG: Generates the cryptographically secure random numbers(rrx) required by the receiver during the authentication handshake.

AES128: Acts as a symmetric block cipher processing 128-bit data blocks using 128-bit cipher keys for robust content encryption and decryption

AUTHENTICATE PROTOCOL: Implements the HDCP receiver side authentication state machine to validate the upstream transmitter's credentials and establish a secure session for protected content reception.

CIPHER GENERATOR: Generates the continuous 128-bit pseudo-random cipher stream required for real time video data decryption

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyCipher Clock Frequency
TSMC 28nm338.15k100Mhz405MHz
SMIC 40nm441.97k100Mhz405MHz
UMC 55nm854.21k100Mhz405MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyCipher clock frequency
Xilinx Vivado 2024.1 Virtex Ultrascale+ VCU118 xcvu9p-flga2104-2L-e44800 LUT's100MHz150MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.