RTC IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech RTC IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Supports to generate alarm interrupt after a time period
Supports to generate seconds, minutes and hours value
Supports configurable seconds, minutes and hours value
Supports calendaring functionality
Supports clock timer functionality
Supports up and down timer counting modes
Supports to hold count value
Supports enabling and disabling of interrupts
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CSR: CSR module has the set of registers used to configure GPIO core, log the GPIO status, program the timeout value for Host and register to store the GPIO data.

CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP and the Core Module acts as the central interconnect hub.

PRESCALER: The Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for RTC.

ALARM: The Alarm module is used to compare the second, minute, hour, day, week, month, year values with current time values and set alarm when all counters value equal.

TIME: The Time module is used to implement the all the counters to load the second, minute, hour, day, week,month, year for time operation.

TIMER: The Timer module is used to implement the timer counter operation based on the threshold value and timer (Up_count or Down_count) mode.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	3.72K	25MHz
UMSC 55nm	7.12K	25MHz
SMIC 40nm	3.94K	25MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	11865 LUT's	25MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.