The SivaKali Tech SDRAM IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.
Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.
Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.
PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.
FEATURES
Supports 100% of SDRAM protocol standard 512Mb_sdr & HY57V56820FT-H.pdf
Supports Internal banks for hiding row access/precharge
Supports Programmable burst lengths: 1, 2, 4, 8, or full page
Supports Auto precharge, includes concurrent auto precharge and auto refresh modes
Supports Self refresh mode:
Standard
Low-power
Supports Auto refresh Supports programmable clock frequency of operation
Supports all types of timing and protocol violation detection
Supports Speed Grade
7E
75 Supports all the SDRAM commands as per the 512Mb_sdr & HY57V56820FT-H.pdf
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the SDRAM IP. Ports of core module are the top level ports for the SDRAM IP.
FSM: Converts system memory requests into SDRAM commands and manages timing, refresh and access sequencing. Handles physical command, address and data signal exchange between the controller and external DRAM device.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
20.45K
10MHz
UMSC 55nm
46.52K
10MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
187.25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
