MIPI APHY DSI-2 SNK PAL IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI APHY DSI-2 SNK PAL IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES

The DSIA interfaces with the A-PHY Data Link Layer via the APPI Interface (As per the A-PHY Specification [MIPI05])
Supports DSIA A-Packet Packing Function
Supports the short, Long packets format and control signals Supports the functional safety, security and HDCP (High bandwidth digital content protection)
Supports Service extension packets
Supports conversion of DSI Long and short packets to SEP
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIPI APHY DSI-2 SINK PAL Ports of core module are the top level ports for the MIPI APHY DSI-2 SINK PAL.

TUNNELING/UNIFYING: This Tunnelimg/Unifying acts as bridge within the Dsi2 Adaptation layer (DSIA) for conversion between SEP (Service extension packets) and Non-SEP. It will operates in any of three modes(Transparent,Legacy,Mixed modes) based on the Reception of SEP or Non -SEP packets.

CHUNK: when receiving a stream of chunks from the packing function, the chunking function uses the order sub-field to reassemble them into their original packets.

PACKER: It extracts the raw SEP application data from the incoming A-packet stream.

UNPACKER: Packing function process the SYNC event msg/response packets and formatting it into a standardized A-packet.It packs the low level packets, so that the pstart (packet start) is always aligned within the A-PHY transmission stream.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System clock frequency	Appi clock frequency
TSMC 28nm	54.27K	125MHz	31.25MHz
UMSC 55nm	109K	125MHz	31.25MHz
SMIC 40nm	82K	125MHz	31.25MHz

FPGA Device and Family	Logic Resources	System clock frequency	Appi clock frequency
AMD-xcvu9p-flga2104-2L-e	9045 LUT's	125MHz	31.25MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.