CORE: The top-level integration layer that interconnects all internal sub-modules and defines the primary IP interfaces for system-level integration.
CSR: CSR contains all Control and Status Registers(CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.
HPD PROCESS: Monitors and generates the Hot Plug Detect signal, asserts IRQ pulses to indicate status changes,detects unplug conditions and co-ordinates required control updates through the AUX channel.
AUX FSM: It manages the auxiliary channel protocol by processing incoming requests from the DisplayPort Transmitter and generating compliant response packets.
LINK TRAINING: It manages the link initialization sequence via the AUX channel. It evaluates clock recovery and channel equalization status to optimize voltage swing and pre-emphasis for a stable connection.
LINK LAYER: The link layer includes the link FSM, Video unpacker, and SDP/Audio unpacker.
LINK FSM: It is responsible for monitoring the incoming audio/video stream,detecting and removing fill symbols and maintaining stream synchronization before forwarding the data to the downstream processing blocks
VIDEO UNPACKER: It Extracts pixel data from the received stream and reconstructs the video based on the configured colorimetry and bits-per-component(BPC).
SDP/AUDIO UNPACKER: It Decodes Secondary Data Packet(SDP) headers to extract audio samples and metadata, reconstructing the audio stream based on the detected sample rate and channel configuration.
DSC: It is an optional module which implements VESA Display Stream Compression(DSC) to decompress incoming video data back into its native, uncompressed pixel format.
HDCP: It is an optional module which ensures content protection by executing authentication protocols with the Source, managing secure key exchange, and performing high-speed decryption.
LOGICAL PHY: The physical coding sublayer(PCS) containing the De-scrambler, 8b10b or 128b132b decoders, RS-FEC, and Gearbox logic.
DE-SCRAMBLER: It Reverses the scrambling polynomial applied at the Transmitter to restore the original data pattern prior to symbol decoding.
8B10B DECODER: It Converts 10-bit symbols back into 8-bit data, recovers control characters, and performs running disparity checks to ensure link integrity.
128B132B DECODER: It Decodes high-efficiency 132-bit blocks into 128-bit data for UHBR rates, restoring the original payload and control information for high-bandwidth links.
RS-FEC(254,250): It is an optional module that performs Reed-Solomon(254,250) decoding to detect and correct transmission errors, effectively removing FEC parity symbols.
GEARBOX: The gearbox module converts the incoming PHY data widths 10-bit,20-bit,40-bit or 80-bit into the internal link layer data width ensuring proper data alignment and reconstruction of the main link stream.
