eMMC SDIO Host Controller IIP

• Compliant with SD Host Controller Specification version 6.0
• Compliant with SDIO Physical Specification version 6.10
• Compliant with Part E1 SDIO specification 4.10
• Compliant with JESD84-B51 Specification and earlier versions
• Compliant with JEDEC eMMC CQHCI for Command Queuing
• Supports different data bus width modes: 1-bit, 4-bit, 8-bit
• Supports Enhanced Strobe
• Supports HS200 and HS400 Modes
• Supports Single byte, Single block ,Multi-block(finite and infinite) transfers
• Supports extended security protocols commands
• Supports SDMA, ADMA2 and ADMA3 modes
• Supports SD Memory, SD I/O card, Combo card
• Supports SPI Bus mode
• Supports all commands/response types
• Supports suspend/resume and read wait
• Supports card detection
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the eMMC SDIO Host Controller IIP. Ports of core module are the top level ports for the eMMC SDIO Host Controller IIP

GENCLK: This module has MMC clock generator logic. The clock divider value is loaded from the register CLOCK_TIMEOUT_CONTROL. This value is from the MMC clock frequency select (either via driver programmed or selected preset value)

CDET: Card Detect State Machine is either the External i_sdif_cd_n or the Internal Signal (Card Detect Test Level) is muxed for Card Detect Logic. The selection is based on the Card Detect Signal Select.

CSR: This module includes all the registers like block size, block count, address,argument ...etc and also it includes card interrupt logic. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. The registers can get its data from both the internal and external system interface. Likewise, it can be retrieved by both the internal and external system interface.

MMC: This module consist of Command generation,Data transmission and Data recieve, Response check, tuning operations

TIMEOUT: For data timeout, when the TXD control or RXD control enables the counting of timeout value, the counter start counting. When the counting is disabled, the counts are reset to zero.

DMA: This module suports three types of DMA. SDMA (Single Operation DMA) performs a read / write SD command operation. ADMA2 performs a read / write SD command operation at a time. ADMA3 can program multiple read / write SD commands operation in a Descriptor Table. ADMA3 is suitable to perform very large data transfer.

CQCT: This module contains task queue logic. The contents of the doorbell FIFO are read out and the tasks to be executed are queued in a task queue FIFO from where the CQ engine works on task. As multiple task bits are set in the doorbell entry, this will be split into individual tasks and enqueued

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.