MIL STD 1553 Controller IIP

Military standard Interface 1553 Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIL STD 1553 Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES

Compliant with MIL STD 1553B specification
Supports Remote terminal, Bus Controller and Bus monitor
Supports configurable length of word length, default 20 bits
Supports configurable length of data bits, default 16 bits
Supports configurable message length per transfer
Supports various mode code and broadcast commands
Supports Manchester II Bi-phase encoding
Bus Controller

Fully compliant with specs
Fully programmable Bus Controller
Bus Controller has 32-bit time count options
Programmable Status Set
Message Format Check
Programmable Inter-Message Gap Time
Programmable Message Timeout
Passed full BC validation testing by 3rd party

Remote Terminal

Programmable different buffer mode for all Subaddress
Sub address based illegal command declaration
Optional temporary buffer
Passed full RT validation testing by 3rd party

Bus Monitor

Monitors all frames on bus and timestamps
Passed full RT validation testing by 3rd party Fully synthesizable

Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIL_STD_1553 IP. Ports of core module are the top level ports for the MIL_STD_1553 IP.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for MIL_STD_1553.

FSM: FSM module generates the MIL_STD_1553 transactions on MIL_STD_1553 based on commands from CSR block. This blocks implements all the features of MIL_STD_1553 specs.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ENCODER: This module is used to drive the data with Manchester encoding and send the data onto the MIL_STD 1553 Interface

DECODER: This module is used to sample the data from the MIL_STD Interface and decodes the Manchester code.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 12nm	38.26K	100MHz
TSMC 28nm	26.07K	100MHz
TSMC 90nm	35.87K	100MHz
TSMC 130nm	35.87K	100MHz
TSMC 180nm	37.24K	100MHz
GF 180nm	27.40K	100MHz
SMIC 40nm	27.29K	100MHz
UMC 55nm	43.45K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	72415 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.