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PMBUS Slave IIP

Power Management Bus Slave IIP

PMBUS Slave IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech PMBUS Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Power v1.5 Management Bus Slave.
  • Compliant with I2C version 7.0 specification.
  • Compliant with version 1.5 of PMBus Bus Specification.
  • Full PMBus Slave Functionality.
  • Supports the following PMBus commands as per Specification,
  • ->Send byte command
  • ->Write byte command
  • ->Write word command
  • ->Read byte command
  • ->Read word command
  • ->Block write command
  • ->Block read command
  • ->Block write and read process call command
  • ->Read 32 protocol
  • ->Group command protocol
  • ->Extended command protocol
  • Supports Zone write and Zone read operation.
  • Supports Slave arbitration.
  • Supports General call address.
  • Supports PMBus device fault management.
  • Supports Packet Error checking(PEC).
  • Supports clock stretching.
  • Supports alert generation.
  • Supports timeout detection and generation.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub modules in PMBus Slave IP (START,STOP,CSR, FSM, ARP and ALERT). Ports of core module are the top level ports of Slave IP.

START: Start module detects the start condition on bus based on i_scl and i_sda line. A HIGH to LOW transition on the i_sda line while i_scl is HIGH defines a START condition.

STOP: Stop is detected based on i_scl and i_sda line. When i_sda line goes from low to high and i_scl remains high is considered as the Stop condition. Master can terminate any transfers by initiating stop and it is detected by the Slave.

FSM: FSM module process PMBus Slave commands once start is detected. FSM responds to PMBus Slave commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the i_sda bus by the Master. The Slave FSM module includes following functionalities as Send byte,Write byte/word,Read byte/word,Read 32 protocol,Block write/read,Block write - block read process call,Group command protocol,Extended command protocol and Zone Read & Zone Write.

CSR: CSR module holds control, status, interrupt, configuration registers for the PMBUS Slave IP which can be accessed via AMBA/Custom interface.

ALERT: When Slave wants to communicate to Master and it is a Slave only device, it pulls the alert output (o_alert) low. The process is enabled from the ALERT block.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencySCL Frequency
TSMC 28nm18.83K10MHz1MHz
TSMC 12nm12.85K10MHz1MHz
TSMC 90nm18.34K10MHz1MHz
TSMC 130nm18.34K10MHz1MHz
TSMC 180nm19.19K10MHz1MHz
GF 180nm13.50K10MHz1MHz
UMC 55nm21.98K10MHz1MHz
SMIC 40nm13.60K10MHz1MHz

FPGA Device and FamilyLogic ResourcesClock FrequencySCL Frequency
AMD Virtex Ultrascale +1986 LUT's10MHz1MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.