CORE: Core module interconnects all the sub-modules in the RapidIO EP IP. Ports of core module are the top level ports for the RapidIO EP IP.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
PHY: The Physical Coding Sublayer (PCS) function is responsible for idle sequence generation, lane striping, scrambling and encoding for transmission and decoding, lane alignment, descrambling and de-striping on reception.
LOGICAL: This module implements RapidIO transaction level functionality, supportinf IO_master and IO_slave operations, doorbell messaging and maintenanc master/slave transaction for device configuration,control and discovery.
TRANSPORT: This module performs packet framing and deframing, manages virutal channel buffering generates protocol response and provides temporary storage through transport buffers to ensure reliable and ordered RapidIO packet delivery.
TX FLOW CONTROL: This module is responsible to initiate the flow control based on the outstanding command in the remote client.It will calculate the outstanding based on the transmitted command count and packet accepted symbol from the remote client.
CSR ARBITER: This module is used to collect the data from both soc slave interface and maintenance master. It transfers the data to CSR registers.
AXI MASTER: AXI Master initiate write/read transfer based on the trigger signals from AXI Master Control logic.
AXI SLAVE: AXI slave module processes write and read transfers simultaneously. This module Supports multiple outstanding request before completing a transfer.
APB SLAVE: This APB Slave module is used to write and read software registers.
