ETHERNET 10BASET1L PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 10BASET1L PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Supports 10BASE-T1L PCS IIP compliant with IEEE standard 802.3-2022 clause 146
Supports MII interface with 10Mbps speed
Supports 33bit Side Stream Scrambler/Descrambler
Supports 4b/3T Encoding/Decoding
Supports 3Level Pulse Amplitude Modulation(PAM3)
Supports full duplex operation
Supports loopback functionality
Supports clause 98 Auto-negotiation
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET 10BASE-T1L MAC IP. Ports of core module are the top level ports for the ETHERNET 10BASE-T1L MAC IP.

TX FSM: The TX FSM module receives the data from MAC MII 10Mbps Interface and performs the scrambling.

4b/3T ENCODER: It will encode the 4 bit MII data into the 3 ternary symbols.

PAM3 ENCODER: It is 3 level Pulse Amplitude Modulation. It converts 3 ternary symbols for line signaling method.

RX FSM: The RX FSM module performs the descrambling of received data and drives in MII interfaces.

3T/4b DECODER: It converts 3 ternary symbols back into the 4bit MII data.

PAM3 DECODER: It converts the voltage levels into ternary symbols.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	PCS Clock Frequency	MII Clock Frequency
TSMC 28nm	56.78K	25MHz	2.5MHz	2.5MHz
UMSC 55nm	73.93K	25MHz	2.5MHz	2.5MHz
SMIC 40nm	62.48K	25MHz	2.5MHz	2.5MHz

FPGA Device and Family	Logic Resources	Clock Frequency	PCS Clock Frequency	MII Clock Frequency
Kintex 7,9463 LUT'S	25MHz	2.5MHz	2.5MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.