CORE: Core module interconnects all the sub-modules in the ETHERNET 1G 10G MAC PCS IP. Ports of core module are the top level ports for the ETHERNET 1G 10G MAC PCS IP.
MAC TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.
MAC TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.
MAC TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC XGMII Interface by encapsulating the Ethernet packet and frame headers.
MAC FLOW CTRL: Initiating the Transmission of pause frame based on the Receive FIFO's threshold or External requests.
MAC PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.
MAC LINK FAULT FSM: LINK FAULT FSM module detects the fault status from the received data and indicates status to the Transmitter.
MAC RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.
MAC RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.
MAC RX CTRL : Receive Control block processes the data from MAC XGMII interface and push the data into RX ASYNC FIFO.
P1G TX FSM: TX FSM module is used to implement both encapsulation and 8B/10B encoding of the GMII data.
P1G TX RATE ADAPTATION: TX Rate Adaptation module receives data from MAC via GMII Interface.
P1G ENC8_8B_10B: To attain DC balance and for clock recovery,ENC8_8B_10B module is used for encoding the eight bit data into more transition ten bit code groups.
P1G TX LPI TIMER: TX LPI Timer module implements the LPI sleep, quiet and refresh timers when LPI is asserted.
P1G RX FSM: RX FSM module is used to maps the 8bit data with the GMII signals.
P1G RX RATE ADAPTATION: RX Rate Adaptation module adapts the data rates for received data.
P1G RX LPI TIMER: RX LPI Timer module implements the LPI quiet, wake and wake fault timers with the LPI reception.
P1G CARRIER SENSE: The carrier sense signal is asserted when if any one of the transmitter starts transmitting frame or receiver starts receiving frame.
P1G SYNC FSM: SYNC FSM module is used to synchronize the 10bit block from the incoming code group based on the Comma Detect.
P1G COMMA DETECT: COMMA DETECT module is used to detect the valid code group on the receive PCS for acquiring alignment with the byte boundary.
P1G DEC_8B_10B: DEC 8B/10B module is used for decoding the ten bit code groups into eight bit data once synchronization lock is attained.
P1G AN FSM: AN FSM module is used to implement for exchanging ability between local device and link partner.
PXG TX FSM: It performs the 64B/66B encoding and scrambled data to transmit.
PXG FEC TRANSMITTER: The FEC transmitter constructs the FEC block of 2080 bits and perform the transcoding, and than scrambling FEC encoded data.
PXG FEC ENCODER: This block performs FEC encoding on the transcoded data and adds the FEC parity at the end of the each FEC block which provides 2112 bit FEC block.
PXG GEARBOX TX FIFO: This FIFO module stores Tx data and process the data with the different read and write clock domain based on the PMA width.
PXG GEARBOX TX: The Tx gearbox module is a digital logic block used to adapt data between two different bus widths and clock frequencies based on the PMA width.
PXG GEARBOX RX: The receive gearbox module is used to adapt the data between two different bus widths and clock frequencies, based on the PMA width.
PXG GEARBOX RX FIFO: This FIFO module stores Rx data and process the data with the different read and write clock domain based on the PMA width.
PXG FEC RECEIVER: The FEC receiver implements the FEC lock FSM and descrambling the FEC data and checks the FEC parity and performs the detranscoding.
PXG FEC DECODER: This block process to check the FEC parity and decode the FEC descrambling data.
PXG BLOCK SYNC: The block synchronizer is used to detect the valid 66bits of data block.
PXG BER: The BER monitor continuously monitors the input data and validates whether it receives a valid sync header.
PXG RX FSM: The RX FSM process the descrambling and 64B/66B decoding of the 66bit valid input data.
PXG AN ARBITER: This block is implemented to AN state transistion to the final resolution, which will be process the information between the DME TX and DME RX to provides the AN process.
PXG AN DME TX: This block handles the transmitter DME pages after that encodes the AN DME page.
PXG AN DME RX: This block after DME page decoding handles the reception of AN DME page.
CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
