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VDC-M Decoder IIP

VESA Display Compression-M Decoder IIP

VDC-M Decoder IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech VDC-M Decoder IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • VDC-M Version 1.2 Decoder
  • Fully compliant with the VDC-M Decoder Versions 1.1 and 1.2 specification and ensures standard-adherent operation across all supported configurations.
  • Supports any integer slice per line values.
  • Supports following maximum bitrates (BPPmax), as follows:
    • 3 × bits_per_component,for 4:4:4
    • 2 × bits_per_component,for 4:2:2
    • 1.5 × bits_per_component,for 4:2:0
  • Supports any combination of bits_per_pixel and slice_width.
  • Supports CSC(Color-space-conversion).
  • Supports the following Picture Hierarchy,
    • Block Level
    • Slice Level
    • Picture Level
  • Supports the following Per-mode Decoding Process,
    • Transform Mode
    • BP Mode
    • MPP Mode
    • Fallback Modes
    • MPPF Mode
    • BP-SKIP Mode
  • Supports rate control (RC) algorithm in the determination of QP.
  • Supports substream de-multiplexing.
  • Supports Syntax parsing for Transform, BP, MPP, MPPF, and BP-SKIP modes.
  • Supports following Hadamard transform applied in the YCoCg color space,
    • 8-point Forward Hadamard Transform
    • 4-point Forward Hadamard Transform
  • Supports PPS decoding.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the VDC-M Decoder IP. Ports of core module are the top level ports for the VDC-M Decoder IP.

CSR: CSR contains all Control and Status Registers (CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.

RATE_BUFFER: Rate buffer temporarily stores the incoming DSC bitstream and regulates data flow to match the decoder processing rate, preventing underflow and overflow.

SUBSTREAM_DEMULTIPLEX: Substream demultiplex module separates the multiplexed bitstream into component substreams(Y, Co, Cg or RGB) and groups for parallel decoding.

ENTROPY_DECODER: VLD module decodes DSU-VLD encoded symbols from the bitstream to recover quantized residual and control information.

RATE_CONTROL: Rate control module manages decoder buffer behavior and synchronizes decoding with the encoder's rate model to ensure compliant and stable reconstruction.

DECODE_MODE: Decoder mode applies the reconstruction algorithm (Transform, BP, MPP and Skip/Flat modes) specified in the bitstream to rebuild each block's pixels.

LINE_BUFFER: Line buffer module stores previously reconstructed pixels from the current and previous lines to support prediction and slice-based processing

CSC: CSC module converts decoded pixels from YCoCg-R to RGB format.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
TSMC 28nm258.38K100MHz200MHz33.33MHz
UMSC 55nm588.45K100MHz200MHz33.33MHz
SMIC 40nm278.56K100MHz200MHz33.33MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
AMD-xcvu9p-flga2104-2L-e43063 LUT's100MHz200MHz33.33MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.