The SivaKali Tech GCI IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant to GCI protocol specification v1.0.
Supports fixed-sized frames.
Supports configurable number of serial lanes as per the specification
Supports 10 bit per lane serdes interface.
Supports training sequence as per spec
Reset the data link layer Supports configurable Tx and Rx long term CRC function per lane
Supports CID and Idle/Pause frames.
Supports Scrambler as per spec
Supports lane reordering as per spec
Supports breaking of frames into sub-frames.
Supports replay and error recovery
Supports polarity inversion
Per lane skew insertion to test lane alignment
Addressable registers
Supports very flexible way to test sync and alignment for state machines at startup
Recovers clock from input serial data stream
Supports all types of error insertion and detection.
CRC errors
Pause frame errors
Bad scrambler state
Lane alignment failure
Disparity errors
Invalid code group insertion
Invalid /K/ characters insertion
Lane Skew insertion
Rich set of configuration parameters to control GCI functionality
On-the-fly protocol and data checking
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the GCI. Ports of core module are the top level ports for the GCI IP.
TRANSMITTER: It performs packing GCI data link or Transaction layer packets with respect of the packet format and performs the scrambling. These packets transmitted in the parallel signals based on the configuration. Also it handles the replay request.
RECEIVER: It performs the lane alignment and deskew lock, then performs the destripping, descrambling and unpacking GCI data link or Transaction layer packets. Receiver also performs the error handling and send the Ack frames.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
SYS Clock Frequency
Serdes Clock Frequency
TSMC 28nm
200K
175MHz
3GHz
1.875GHz
UMSC 55nm
243K
175MHz
3GHz
1.872GHz
SMIC 40nm
274K
175MHz
3GHz
1.872GHz
FPGA Device and Family
Logic Resources
Clock Frequency
SYS Clock Frequency
Serdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e
50220 LUT's
175MHz
195MHz
175MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
