Automotive CAN Analog PHY IP

High-Speed In-Vehicle Networking with CAN XL & FD

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Automotive CAN Analog PHY IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. High-performance analog front-ends engineered for the most demanding high-speed connectivity standards. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Broad Foundry Support: Silicon-proven and optimized for leading foundries including TSMC, SMIC, UMC, and GlobalFoundries.

Robust Fault Tolerance: Integrated protection against bus shorts, thermal overload, and high-voltage DC faults.

Functional Safety Ready: Developed with ISO 26262 standards in mind, providing the reliability required for automotive and industrial missions.

Ultra-Low Power & Area: Industry-leading PPA (Power, Performance, Area) metrics achieved through meticulous circuit design and layout.

FEATURES

Fully compliant with ISO 11898-2:2024 (CAN XL FAST/SIC), ISO 11898-2:2016, and SAE J2284.
Supports next-gen CAN XL data rates up to 20 Mbps (FAST) and 8 Mbps (SIC).
High-speed CAN FD support up to 8 Mbps with optimized symmetry and timing margin.
Exceptional Noise Immunity: Wide Common-Mode Range (CMR) for robust industrial/automotive operation.
Robust bus protection: Up to ±58V DC fault tolerance and superior ESD robustness (>8kV HBM).
Intelligent power management: Ultra-low power Standby and Sleep modes with WUP/WUF support.
Advanced fail-safe features: TXD dominant timeout, thermal protection, and undervoltage lockout.
AEC-Q100 Grade 1/0 qualified for extreme temperature operation (-40°C to +150°C).
Flexible digital I/O interface (1.7V to 5.5V) for direct connection to low-voltage MCUs.

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

GDSII Layout (Hard Macro).
LEF Abstract for Place & Route.
CDL Netlist for LVS and Simulation.
LIB (.lib) Timing, Power, and Noise Models.
Verilog Behavioral/Functional Models.
Integration Guide and Application Notes.
Characterization and Simulation Reports.
LVS, DRC, and ERC Verification Reports.
ISO 26262 Safety Manual (SAM) and FMEDA (for Automotive).