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MIPI D-PHY Analog PHY IP

High-Bandwidth Mobile Interfaces

MIPI D-PHY Analog PHY IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI D-PHY Analog PHY IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • Dual-mode PHY: Fully compliant with MIPI D-PHY v2.5 .
  • Supports data rates up to 9.0 Gbps per lane (D-PHY) .
  • Ultra-low power performance: Optimized for mobile with < 1.0 pJ/bit energy efficiency.
  • Support for High-Speed (HS), Low-Power (LP), and Ultra-Low Power Escape (ULPS) modes.
  • Integrated adaptive ISI calibration, skew compensation, and transmit de-emphasis.
  • Standard MIPI PHY Protocol Interface (PPI) for easy integration with CSI-2 and DSI-2 controllers.
  • Supports lane/trio swapping, polarity inversion, and flexible input clock references.
  • Functional Safety: AEC-Q100 qualified and ASIL-B ready for automotive vision systems.
FUNCTIONAL DESCRIPTION
ASIC AND FPGA IMPLEMENTATION
LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • GDSII Layout (Hard Macro).
  • LEF Abstract for Place & Route.
  • CDL Netlist for LVS and Simulation.
  • LIB (.lib) Timing, Power, and Noise Models.
  • Verilog Behavioral/Functional Models.
  • Integration Guide and Application Notes.
  • Characterization and Simulation Reports.
  • LVS, DRC, and ERC Verification Reports.
  • ISO 26262 Safety Manual (SAM) and FMEDA (for Automotive).