The SivaKali Tech SafeSPI Master IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.
Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.
Proven Reliability: Thousands of production deployments ensuring rock-solid stability.
Driver Support: Includes bare-metal and Linux drivers to accelerate software development.
FEATURES
Supports full SafeSPI Master Functionality
Supports mode fault error flag with CPU interrupt capability
Supports serial clock with programmable polarity and phase
Supports flexible Serial clock generation
Supports any kind of SPI transactions to access any kind of SPI slave device
Supports individually Controllable pins to drive chip-select
Supports all SafeSPI Transfers as per the Specification.
Supports all SafeSPI Timing Standards.
Supports in-frame and out-of-frame communication.
Supports 32bit and 48bit frame length.
Supports CRC calculation for in-frame and out-of-frame command/response.
Supports Flexible Data and Sensor format.
Supports 32Bit and 48Bit Mode by CS signal and sensor address.
Support interrupt generation based on threshold
Supports Control and Status Registers to configure the module settings
Supports configurable Transmit/Receive Data FIFO
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core Module interconnects all the sub-modules in the SafeSPI IP. Ports of core module are the top level ports for the SafeSPI IP.
FSM: FSM Module generates the SafeSPI transcations on SafeSPI Master based on commands from CSR block. This blocks implements all the features of SafeSPI specifications.
CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
DMA Clock Frequency
Serial Clock Frequency
TSMC 28nm
17.45K
100MHz
100MHz
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
