SuperIO IIP

• SuperIO Controller Feature
• Supports SuperIO seven logical devices corresponding to seven individualfunctions
• Supports SuperIO sending messages between the Host and the SoC
• Supports thresholds to generate SuperIO interrupt
• Supports SuperIO Control and Status Registers to configure the modules
• Supports full UART IP functionality
• Supports full GPIO IP functionality
• Supports full Mailbox IP functionality
• Supports full SWC IP functionality
• UART Feature
• Compliant with Standard UART 16550 Specification
• Full UART Functionality
• Transmit and receive commands allow the user to transmit and receive UART data
• Supports Character Mode, FIFO Mode and Extended FIFO Mode
• Supports 5, 6, 7 and 8 data bits on serial inputs and output with 1,1.5 or 2 stop bits
• Supports address filed in asynchronous frame format
• Parity, Framing and Overflow error detection
• Programmable Baud rates are 1800bps, 2400bps, 4800bps, 9600bps, 19200bps, 28800bps, 38400bps, 57600bps, 76800bps, 115200bps, 230400bps, 460800bps, 576000bps, 921600bps, 1843200bps, 3686400bps
• Full duplex operation
• Fully configurable serial interface
• Configurable receive FIFO depth
• Automatic Data Formatting and status generation
• Interrupt Controller
• Modem Control interface with CTS,RTS,DSR,DTR,RI and DCD signals
• Programmable hardware flow control
• Supports multi-processor mode and low power mode
• Line break detection and generation
• On-the-fly protocol and data checking
• Fully synthesizable
• Static synchronous design
• Positive Edge clocking and no Internal states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller device
• GPIO Feature
• Support Port 80h/81h redirect to two GPIO Groups for LED indicator
• Support Port 80h/81h redirect to Serial GPIO Port1 & Port2 for LED indicator
• Mailbox Feature
• Supports 32 general purpose Mailbox registers in each node
• Supports sending messages between the Host and the SoC
• Supports full Mailbox transmitter functionality
• Supports full Mailbox receiver functionality
• Supports masking of Mailbox interrupts
• Supports thresholds to generate interrupt
• Supports configurable Transmit/Receive data FIFO
• Supports mode fault error flag with CPU interrupt capability
• Supports Control and Status Registers to configure the module
• SWC (ACPI) Feature
• Support ACPI/PM logic
• SMI Support
• SCI Support
• SerIRQ Support
• S3# and S5# Support(ACPI Interface GPIO(S3 & S5)
• Programmable Wake-up Events
• Plug and Play Register Set
• Power Supply Control
• Power Button Control– GPIO Support

CORE: Core module interconnects all the sub-modules in the SUPERIO IP. Ports of core module are the top level ports for the SuperIO Controller IP.

UART: UART module implements UART core

GPIO: GPIO module implements GPIO controller

MAILBOX: MAILBOX module implements Mailbox core

ACPI: ACPI module implements ACPI core

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.