The SivaKali Tech LPC Device SoC Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with version 1.1 LPC Specification
Full LPC Device SoC Bridge functionality
Supports the following operations
Memory read and write
I/O read and write
DMA read and write
Bus Master memory read and write
Bus Master I/O read and write
Firmware memory read and write
TPM read and write
Supports all transfer sizes
Supports 128 Bytes for Firmware read
Support a variable number of wait-states
Supports Sync timeout detection and abort transfer
Supports Sync field based error detection and reporting
Supports wake-up and other power state transitions
Peripheral is capable of responding to all types of LPC transactions
Supports Abort Mechanism as per specification
Supports soft reset
Supports Reset policy
Supports SoC Master Read/Write capability
Supports SoC Slave
Supports LPME#, LPCPD#, CLKRUN# Power management signals
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the LPC Device Soc bridge IP. Ports of core module are the top level ports for the LPC Device Soc bridge IP.
FSM: FSM module receives the transactions from the LPC Bus and process the serial data. This blocks implements all the features of LPC specs. Transmission occurs independently any action of the Device module.
LDRQ: This module controls the LDRQ# lines to handle the DMA channel and Bus Mastering, which will be requested from LPC devices. LDRQ# is synchronous with LCLK.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
BRIDGE: The Module BRIDGE is used to process bridge commands from/to LPC Host. This module is interacts with SoC Master.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
Protocol Clock Frequency
TSMC 28nm
10.75K
100MHz
33MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
17913 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
