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ETHERNET 1G MAC IIP

ETHERNET 1G MAC IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 1G MAC IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Compliant with IEEE 802.3.2022 standard specifications
  • Supports Full duplex and Half duplex mode of operation
  • Supports GMII and MII Interfaces
  • Supports MDIO Clause 22 Interface
  • Supports Programmable Inter Packet Gap(IPG) and Preamble length
  • Provides detailed statistics as per the specs
  • Supports 802.3.az Energy Efficient Ethernet(EEE)
  • Supports 802.3.1Q and 802.3.1ad VLAN
  • Supports Wake-on-LAN
  • Supports Control frame and Jumbo frame
  • Supports FCS (CRC) transmission and reception
  • Supports Pause frame-based flow control in full - duplex mode Supports transmit and receive FIFO interface
  • Supports Loopback Functionality
  • Optional Supports RMII, RGMII and TBI interfaces
  • Optional feature TCP/UDP/IP offload support
  • Optional feature PTP 1588 support
  • Optional feature DMA support for both transmit and receive side
  • Supports AXI stream Interface for System Interface
  • In house UNH compliance tested Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • The following features are supported for TCP/IP/UDP offload engine
  • Fully functional TCP/IP end point
  • UDP support
  • 1Gbps sustained line-rate performance
  • Uses external Memory for payload buffering Basic DHCP Client for IP address configuration
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET 1G MAC IP. Ports of core module are the top level ports for the ETHERNET 1G MAC IP.

TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

GMII/MII TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

GMII/MII RX FSM: The RX FSM module receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL: Receive Control block processes the data from MAC 1G interface and push the data into RX ASYNC FIFO

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencySystem Clock FrequencyMAC Clock Frequency
TSMC 28nm22.92K167.66MHz167.66MHz125MHz
UMSC 55nm44.46K167.66MHz167.66MHz125MHz
SMIC 40nm34.12K167.66MHz167.66MHz125MHz

FPGA Device and FamilyLogic ResourcesClock FrequencySystem Clock FrequencyTransmitter Clock FrequencyReceiver Clock Frequency
Zynq - 7 ZC706 evaluation board6662 LUT's167.66MHz167.66MHz125MHz125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.