I2S Controller IIP

Inter IC Sound Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech I2S Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

I2S Controller IIP
Fully compliant with the Philips I2S Bus Specification and ensures standard-adherent operation across all supported configurations.
Supports 2 to 64 audio channels.
compatible audio sampling rate of 8kHz, 16kHz, 24kHz, 32kHz, 48kHz, 96kHz and 192kHz.
Supports configurable audio data width 8, 16, 24, 32 and 64.
Programmable word select resolution (8 to 64 clock cycles) in master mode.
Supports both Master and Slave modes with transmit and receive capability.
Supports multiple audio data formats

I2S format
TDM format

Bidirectional operation through two unidirectional serial data lines.
Programmable delayed capture and driving of serial data.
Selectable four reference clock sources for bit clock generation with programmable clock divider.
64 deep 32-word FIFOs (left/right: transmit/receive).
Programmable FIFO threshold levels for interrupt or DMA request generation.
Additional interrupts for transmit FIFO under run and receive FIFO over run with separate enables.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

TX PRESCALAR: TX Prescalar module divides the input clock based on the programmed prescalar value. It generates the required serial clock for the transmitter operations.

TX FSM: TX FSM module controls the I2S transmitter data flow by managing bit order, protocol mode , SD delay , clock mode and clock polarity according to the current I2S processing phase.

RX PRESCALAR: RX Prescalar module divides the input clock based on the programmed prescalar value. It generates the required serial clock for the receiver operations.

RX FSM: RX FSM controls the I2S receiver data flow by managing bit order, protocol mode , SD delay , clock mode and clock polarity according to the current I2S processing phase.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	I2S Clock Frequency
TSMC 28nm	4.91K	100MHz	12.288MHz
SMIC 40nm	5.19K	100MHz	12.288MHz
UMC 55nm	8.50K	100MHz	12.288MHz

FPGA Device and Family	Logic Resources	System Clock Frequency	I2S Clock Frequency
AMD-xcvu9p-flga2104-2L-e	865 LUT's	100MHz	12.288MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.