CORE: Core module interconnects all the sub modules in I3C Slave AXI Bridge IP (START, STOP, RESTART pattern, EXIT pattern, FSM, CSR). Ports of core module are the top level ports of I3C Slave AXI Bridge IP.
CSR: CSR module holds control, status, interrupt, configuration registers for the I3C Slave To AXI Bridge IP which can be accessed via AMBA/Custom interface.
FSM: FSM module process MIPI I3C commands once Start is detected. FSM responds to MIPI I3C commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the MIPI bus by the Master. The Slave FSM module includes following functionalities as Legacy I2C write/read transactions,I3C SDR transaction,Hot-Join transaction,In-Band-Interrupt transaction,I3C HDR-DDR transaction and Error detection.
HDR Exit Restart module: The HDR Restart Pattern used to send multiple messages in HDR Mode. When the I3C Bus is in a HDR Mode, an HDR Command can be sent to a Slave, and the HDR Restart Pattern can be used to send another HDR transfer continuosly, without exiting the current HDR Mode between the HDR Commands. All I3C Slaves shall detect and respond to the HDR Restart Pattern. HDR exit pattern is used to leave the HDR mode, and entering back to SDR mode. All I3C slaves shall detect and respond to the HDR exit pattern.
STOP: All transitions terminates with stop condition. Stop is detected based on SCL and SDA line. When SDA line goes from LOW to HIGH and SCL remains high is considered as the Stop condition. Master can terminate any transfers by initiating stop and it is detected by the Slave.
START: Initially SCL and SDA lines remains High, all transactions begin with a START condition. Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition Master initiates the start, it is detected by Slave. At certain condition (in case of hot join and IBI) Slave can initiate start. Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. Repeated start condition is same as start condition, it is detected before stop condition. We can continue the further transfers without stop.
DMA: External host (I3C Master) can access the internal address space by sending I3C read/write commands to I3C slave block. I3C slave engine shall decode I3C commands and do appropriate AXI Master transactions to Read/Write data from/to SRAM or on chip registers. Various command codes are 0x00 – Read command to AXI master,0x01 – Write command to AXI master,0x02 – Mailbox Push,0x03 – Mailbox Pop,0x04 – Shutdown,0x05 – Sleep,0x06 – Wakeup,0x07 – Reset,0x08 – Local register write and 0x09 – Local register read
