Madhya-V3 Medium RISC-V CPU

Balanced Performance Application Core

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Madhya-V3 Medium RISC-V CPU is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Versatile processor cores designed for everything from ultra-compact IoT sensors to high-performance edge computing. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High-Efficiency Pipeline: Advanced multi-stage pipelines optimized for maximum performance-per-watt, outpacing standard legacy architectures.

Scalable ISA: Full support for industry-standard instruction sets (8051, RISC-V) with modular extensions for floating-point, vectors, and security.

Functional Safety (ISO 26262): Available with ASIL-D ready features including hardware redundancy (DMR/TMR) and comprehensive fault-injection testing.

Advanced Debug & Trace: Integrated on-chip debugging solutions compatible with industry-standard development tools for rapid software bring-up.

FEATURES

Full support for RV32GC (IMAFDC) instruction set extensions.
Deep 5-stage in-order pipeline with advanced dynamic branch prediction.
Integrated Single-precision Floating-Point Unit (FPU).
Linux-ready Memory Management Unit (MMU) with SV32 support.
Configurable L1 Instruction and Data caches (8KB to 64KB).
Supports User, Supervisor, and Machine privilege modes.
Physical Memory Protection (PMP) for enhanced system security.
High-speed AXI4 or AHB-Lite system bus interfaces.
Scalable multi-core configurations with cache coherency.

FUNCTIONAL DESCRIPTION

ASIC AND FPGA IMPLEMENTATION

Process Node	Frequency (GHz)	Performance (CoreMark/MHz)
7nm FinFET	1.5	3.5
12nm FinFET	1.2	3.3
28nm HPC+	0.8	3.1

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.