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VESA DSC Encoder IIP

VESA Display Stream Compression Encoder IIP

VESA DSC Encoder IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech VESA DSC Encoder IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • VESA DSC Version 1.2a Encoder
  • Fully compliant with the VESA Display Stream Compression Encoder Versions 1.1, 1.2, 1.2a and 1.2b specification and ensures standard-adherent operation across all supported configurations.
  • Backward compatible with DSC v1.1.
  • Dynamically supports slice configurations of 1, 2, 4, 8, 12, 16, 20, 24.
  • Supports configurable input pixel processing of 1 pixels per clock.
  • Supports maximum display resolution up to 8K.
  • Supports all the video formats which are mentioned in Display Stream Compression up to 1.2b version,
  • ->RGB (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:2 simple (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:2 native (8, 10, 12, 14 and 16 bits per component)
  • ->YCbCr 4:2:0 native (8, 10, 12, 14 and 16 bits per component)
  • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    • Block Prediction (BP)
    • Midpoint Prediction (MPP)
    • Indexed Color History (ICH)
  • Supports programmable compressed bit rate of 8bpp and higher (6bpp and higher for 4:2:0 pictures).
  • Supports Output Buffering compatible with transport stream over video interfaces like HDMI2.1, MIPI DSI and DisplayPort.
  • Verified with VESA DSC 1.2a C model using sample images.
  • Supports PPS 128 bytes block decoding.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the DSC ENCODER IP. Ports of core module are the top level ports for the DSC ENCODER IP.

CSR: CSR contains all Control and Status Registers (CSRs). It decodes CPU-driven configuration commands and maps them to functional output signals across the IP.

CSC: CSC module converts input pixels from RGB to YCoCg-R to improve compression efficiency.

SLICE_BUFFER: Slice buffer module stores pixels for slice based processing, enabling low latency and independent encoding of each slice.

FLATNESS_CHECKER: Flatness checker module determines whether upcoming pixel groups are visually flat by analyzing pixel variation within a supergroup and generates a QP override to improve compression quality in low detail regions.

RATE_CONTROL: Rate control module controls bit allocation and quantization parameters to maintain constant output bit rate and buffer compliance.

PREDICTION: Prediction module generates predicted pixel values using MMAP, Block Prediction, Midpoint Prediction and Index Color History and computes the prediction residuals for entropy encoding.

LINE_BUFFER: Line buffer module holds reconstructed pixels from previous samples/lines to support Prediction, Flatness Detection, Rate Control, Index Color History(ICH).

VLC_ENTROPY_ENCODER: VLC module encodes quantized residuals and syntax elements using DSU-VLC to reduce bitstream size.

SUBSTREAM_MULTIPLEX: Substream multiplex module combines component substreams(Y, Co, Cg) into a single slice bitstream according to the DSC bitstream syntax.

RATE_BUFFER: Rate buffer module converts the variable length encoded output into a constant bit rate DSC bitstream suitable for transmission.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
TSMC 28nm222.68K100MHz200MHz33.33MHz
UMSC 55nm443.45K100MHz200MHz33.33MHz
SMIC 40nm303.90K100MHz200MHz33.33MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyPixel Clock FrequencyBitstream Clock Frequency
AMD-xcvu9p-flga2104-2L-e37113 LUT's100MHz200MHz33.33MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.