ROCE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ROCE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Compliant with ROCE Specification v2
Supports full InfiniBandTM Architecture Specification Volume 1 and Supplement to InfiniBandTM Architecture Specification Volume 1 Release 1.2.1 RoCE specification.
Supports full 802.3 10G/25G/40G/50G/100G/200G/400G Ethernet specification.
Supports DMA support for both transmit and receive side
Supports the RoCEv1 and RoCEv2
Supports the following Infini Band transport services
--> Reliable Connection
--> Reliable Datagram
--> Unreliable Connection
--> Unreliable Datagram
Supports the following upper layer protocols
--> IPV4
--> IPV6
--> UDP
Supports the following Transport functions
--> SEND
--> RESYNC
--> RDMA READ
--> RDMA WRITE
--> ATOMIC
Supports the following Transport Headers
--> Base Transport Header
--> Extended Transport Header
Supports priority flow control of Ethernet
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ROCE IP. Ports of core module are the top level ports for the ROCE IP.

TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

GMII/MII TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.

GMII/MII RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL: Receive Control block processes the data from MAC 1G interface and push the data into RX ASYNC FIFO

RDMA QUEUES: The RoCE IP implements RDMA queues like Receive Queue (RQ), Send Queue (SQ), and Completion Queue (CQ).These queues are referred to as Queue Pairs or QPs.

ROCE TX: The TX Path consists of outgoing RDMA READ, RDMA WRITE transactions, and ACK packets for incoming RDMA SEND/WRITE requests and responses for incoming RDMA READ requests.

ROCE RX: The RoCE RX Path gets the packet data from the MAC through the AXI4-Stream interface. All incoming packets are validated and all packet headers that fail packet validation are sent to the error buffer.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
TSMC 28nm	42.92K	167.66MHz	167.66MHz	125MHz
UMSC 55nm	94.46K	167.66MHz	167.66MHz	125MHz
SMIC 40nm	64.12K	167.66MHz	167.66MHz	125MHz

FPGA Device and Family	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
Zynq - 7 ZC706 evaluation board	6662 LUT's	167.66MHz	167.66MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.