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JESD204B Transmitter IIP

JEDEC Serial Data Interface 204B Transmitter IIP

JESD204B Transmitter IIP

Overview

1. Data Mode

2. Test Mode

COMPETITIVE ADVANTAGE

The SivaKali Tech JESD204B Transmitter IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with JESD204 specification JESD204A, JESD204B.01
  • Full JESD204B transmit functionality
  • Supports data rate up to 12.5 Gbps
  • Supports programmable clock frequency up to 12.5 GHz
  • Supports up to Subclass 0, 1, 2
  • Supports up to Version A and B
  • Supports 1 to 8 lanes
  • Supports 1 to 64 converters per transmitter
  • Supports frame sizes of 1, 2, 4, 8 and 16 octets per frame
  • Supports HD-mode
  • Supports 1 to 32 bit data width per converter
  • Supports CF = 0 and 1 control words per frame clock period per link
  • Supports 0 to 3 control bits per sample
  • Supports 1 to 8 samples per converter
  • Supports 1 to 32 frames per multiframe
  • Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample
  • Supports 0 to 15 Bank ID (BID)
  • Supports 0 to 255 Device Identification Number (DID)
  • Supports 0 to 7 Lane Identification Number (LID)
  • Supports different Serdes interfaces 10, 20, 40, 60 bits and custom bits per lane
  • Continuous sequence of a scrambled jitter pattern (JSPAT) and modified random pattern (modified RPAT)
  • Continuous sequence of either /D21.5/ or /K28.5/ characters for code group synchronization
  • Repeated transmission of a lane alignment sequence, preceded by a code group synchronization sequence
  • Scrambler can be enabled or disabled
  • Supports 8b/10b encoding
  • MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the JESD204B Receiver IIP. Ports of core module are the top level ports for the JESD204B Receiver IIP

TRANSPORT LAYER: The transport layer maps the conversion samples to non-scrambled octets. A set of samples and/or partial samples is grouped into a frame of F octets. Each sample is received as a group of N' bits, consisting of N data bits, optional control bits and optional tail bits

LINK LAYER: Link The transmitters emit a stream of /K/= /K28.5/ symbols upon receiving sync request from the receiver. After achieving synchronization, the ILA multiframe sequence is sent and then data is sent

LANE: Lane module is used to encoded the data vary based on the serdes interface when Lane encoder is enabled or un-encoded data sent

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyCharacter Clock FrequencySerdes Clock Frequency
TSMC 12nm215K100MHz312.5 MHz1.25 GHz
TSMC 28nm150K100MHz312.5 MHz1.25 GHz
UMSC 55nm245K100MHz312.5 MHz1.25 GHz
SMIC 40nm160K100MHz312.5 MHz1.25 GHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.