CORE: Core module inter connects all the sub modules in SMBus slave IIP (START, STOP,CSR, FSM, ARP and ALERT). Ports of core module are the top level ports of Slave IP.
FSM: FSM module process SMBus Slave commands once start is detected. FSM responds to SMBus Slave commands (ACK/NACK for Write & Read transfer and Read data for read transfer) only if Slave address is matched with the address driven on the i_sda bus by the Master. The Slave FSM module includes following functionalities as Quick command,Send /receive byte,Write byte/word,Read byte/word,Process call,Block write/read,Block write - block read process call,Write 32 protocol,Write 64 protocol,Read 32 protocol and Read 64 protocol.
CSR: CSR module holds control, status, interrupt, configuration registers for the SMBUS Slave IP which can be accessed via AMBA/Custom interface.
ALERT: When slave wants to communicate to master and it is a slave only device, it pulls the alert output (o_alert) low. The process is enabled from the ALERT block.
START: Initially i_scl and i_sda lines remains High, all transactions begin with a START condition. Start module detects the start condition on bus based on i_scl and i_sda line. A HIGH to LOW transition on the i_sda line while i_scl is HIGH defines a START condition Master initiates the start, it is detected by Slave. Repeated start condition is same as start condition, it is detected before stop condition. We can continue the further transfers without stop condition.
STOP: All transition terminates with stop condition. Stop is detected based on i_scl and i_sda line. When i_sda line goes from low to high and i_scl remains high is considered as the Stop condition. Master can terminate any transfers by initiating stop and it is detected by the Slave.
