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UART CONTROLLER IIP

UART CONTROLLER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech UART CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. The backbone of system control and peripheral connectivity for any SoC. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Ultra-Low Gate Count: Extremely efficient implementation, negligible impact on total SoC area.

Simple Integration: Standard AMBA (APB/AHB) or AXI-Lite interfaces for plug-and-play system connectivity.

Proven Reliability: Thousands of production deployments ensuring rock-solid stability.

Driver Support: Includes bare-metal and Linux drivers to accelerate software development.

FEATURES
  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Compliant with Standard UART 16550 Specification
  • Full UART Functionality
  • Transmit and receive commands allow the user to transmit and receive UART data
  • Supports Character Mode, FIFO Mode and Extended FIFO Mode
  • Supports 6, 7 and 8 data bits on serial inputs and output with 1,1.5 or 2 stop bits
  • Parity, Framing and Overflow error detection
  • Programmable Baud rate from 110 bps to 115.2 kbps
  • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO
  • Full duplex operation
  • Fully configurable serial interface
  • Supports character width from 1 bit to 32 bits
  • Configurable receive FIFO depth
  • Programmable Word length, Stop bits and Parity
  • Automatic Data Formatting and status generation
  • Interrupt Controller
  • Modem Control interface with CTS,RTS,DSR,DTR,RI and DCD signals
  • Provides bidirectional IRDA 1.4 Interface
  • Programmable hardware flow control
  • GPIO are supported using read and write commands
  • Line break detection and generation
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the UART Controller IP. Ports of core module are the top level ports for the UART Controller IP.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

TPRESCALER and RPRESCALER: These modules is used to divide the system clock based on the given prescaler value to derive the serial clock input for UART.

TFSM: TFSM module is responsible for UART data transmission based on commands from CSR block.

RFSM: TFSM module is responsible for UART data reception based on commands from CSR block.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 12nm7.54K50MHz
TSMC 28nm5.33K50MHz
TSMC 90nm7.60K50MHz
TSMC 130nm7.60K50MHz
TSMC 180nm8.13K50MHz
GF 180nm5.68K50MHz
SMIC 40nm5.65K50MHz
UMSC 55nm9.27K50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e1241 LUT's50MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.