ETHERNET MDIO MASTER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET MDIO MASTER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Compliant with IEEE Standard 802.3.2022 specification
Supports MDIO Clause 22 (Direct) and Clause 45 (Indirect)
Supports configurable all MDIO address
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

Clause 22: Generates the MDC clock and drives all read/write transactions on the MDIO bus using a 5-bit PHY address and 5-bit register address (32 registers max). It Initiates every frame and controls bus direction.

Clause 45: Drives extended MDIO frames using 4 opcodes (ADDRESS / WRITE / READ / POSTREAD) with a 5-bit device address (DEVAD) and 16-bit register address — giving access to 32 devices × 65536 registers. Manages multi-device PHYs (PMA/PMD, PCS,PHY XS, DTE XS) on a single MDC/MDIO bus.

CORE: Core module interconnects all the sub-modules in ETHERNET MDIO Master IP. Ports of core module are the top level ports for the ETHERNET MDIO Master IP.

MDC: This module is clock divider that scales the high speed system clock to a stable clock frequency and it provides the reference timing used by the PHY to sample all management data

MDIO: This module manages the Bi-directional data line using a tri-state buffer to switch between driving bits and receiving bits. It ensures data transitions occur only when the MDC is low to prevent bus contention.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	MDIO Clock Frequency
TSMC 28nm	1.57K	167.66MHz	41.66MHz
UMSC 55nm	3.14K	167.66MHz	41.66MHz
SMIC 40nm	2.24K	167.66MHz	41.66MHz

FPGA Device and Family	Logic Resources	Clock Frequency	MDIO Clock Frequency
AMD-xcvu9p-flga2104-2L-e	261 LUT's	167.66MHz	41.66MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.